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description the CXD2131Q is an ic that encodes and decodes video aspect ratio identification signal (conforming to eiaj standard cpx-1204) in the vertical blanking interval of an ntsc video signal. features the processing formerly carried out by the two chips cxa1727q and cxd2122aq has been consolidated into this one chip. both microcomputer serial interface and i 2 c interface functions are built in. applications wide-screen televisions, vcrs, muse-ntsc converters structure silicon gate cmos ic absolute maximum ratings supply voltage v dd v ss ?0.5 to +7.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 4.5 to 5.5 v operating temperature topr ?0 to +70 ? ?1 CXD2131Q e94z26-st video aspect ratio identification signal encoder/decoder sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 32 pin qfp (plastic)
? 2 CXD2131Q block diagram 1 5 2 7 2 8 2 9 3 0 v c r 4 - l i n e s e r i a l i n t e r f a c e t i m i n g s i g n a l g e n e r a t o r d e c o d e r c r c c c h e c k d a t a v a l i d i t y c r i t e r i o n e n c o d e r 1 / 4 f r e q u e n c y d i v i d e r s y n c s e p a r a t o r c h i p c l a m p p e d e s t a l c l a m p d a t a s l i c e r s y n c s e p a r a t o r c h i p c l a m p p e d e s t a l c l a m p d a t a s l i c e r 2 0 2 1 2 1 0 1 1 1 2 1 3 1 7 1 8 3 1 3 2 1 6 6 7 3 4 9 i 2 c b u s i n t e r f a c e 1 4 2 1 4 c r c c - o k v a l i d 1 4 1 2 1 4 2 2 i n t e r n a l c l o c k o 1 6 4 o l b x c r c o s r o t x c s s c l k s r i n s c l s d a m c o n c s y c v i n 1 1 v i n 1 2 v i n 2 1 v i n 2 2 v i n 3 v o u t i 1 6 4 p r t c / i l b x s e l x t x o x i
? 3 CXD2131Q pin description analog ground. clock fsc/4 fsc switching; 4 fsc at 1. oscillator connection (fsc or 4 fsc). oscillator connection or clock input. digital ground. encoder input; 16:9 at 1, 4:3 at 0. fixed to 0 when not used. microcomputer interface switching; 0 = i 2 c, 1 = serial. [encoder input; 1 = letter-box, 0 = normal]. digital system power supply. microcomputer interface exists; 1 = yes, 0 = no. serial interface output to microcomputer [fixed to 0]. select from microcomputer [encoding exists; 1 = yes]. clock from microcomputer [decoder input channel switching]. data from microcomputer [decoder line 1 existence]. standby and reset at 0. crcc check monitor output. composite sync monitor output. i 2 c bus clock. i 2 c bus data. digital ground. decoder output; 1 = letter-box, 0 = normal. decoder output; 16:9 at 1, 4:3 at 0 (decode slicer output). test input; normally connected to vss; when 1, pin 21 switches to the function in parentheses ( ). test input; connect to vss. analog bias current setting. analog bias current setting. analog system power supply. sync separation input. decoder data slicer input. sync separation input. decoder data slicer input. encoder input. encoder output. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 av ss selxt xo xi v ss i164 prtc [ilbx] v dd mcon srot xcs [oe] sclk [isel] srin [lnj1] xrst crco csyc scl sda v ss olbx o164 (dthi) tst1 tst2 iset1 iset2 av dd vin11 vin12 vin21 vin22 vin3 vout i o i i i i i/o i i i i o o i i/o o o i i i i i i i i i o analog ttl cmos cmos ttl ttl ttl ttl * 1 ttl ttl ttl ttl * 2 cmos cmos cmos * 2 cmos * 2 , 4 cmos cmos ttl * 3 ttl * 3 analog analog analog analog analog analog analog analog analog pin no. symbol i/o i/o level description * 1 three-state * 2 schmitt input * 3 with pull-down resistor * 4 open drain note 1) in microcomputer-free mode when mcon = 0, pin 7 and pins 10 to 13 switch to the functions in parentheses [ ]. at this time connect srot (pin 10) to vss. note 2) when tst1 = 1, pin 21 switches to the function in parentheses ( ).
? 4 CXD2131Q electrical characteristics dc characteristics (logic section) (v dd = 5.0v, v ss = 0v, ta = 25 c) item symbol condition min. typ. max. unit remarks output voltage output voltage output voltage input voltage input voltage input voltage input leak current output leak current current consumption v oh v ol v oh v ol v ol v ih v il v ih v il v ih v il i i i oz i dd i oh = ?ma i ol = 4ma i oh = ?ma i ol = 3ma i ol = 4ma v in = either v ss or v dd v in = either v ss or v dd v dd ?0.8 v dd /2 2.2 0.7 v dd 0.8 v dd ?0 ?0 15 0.4 v dd /2 0.4 0.8 0.3 v dd 0.2 v dd +10 +40 v v v v v v v v v v v a a ma except for pins 3 and 18 pin 3 only pin 18 only except for pins 4, 17 and 18 pin 4 only pins 17 and 18 only except for pins 4, 10, 22 and 23 pin 10 only sum of pins 8 and 26 ac characteristics (v dd = 5.0v, v ss = 0v, ta = 25 c) item symbol condition min. typ. max. unit remarks clock frequency serial transmission clock frequency fxi fsclk selxt (pin 2) = v ss selxt (pin 2) = v dd mcon (pin 9) = v dd prtc (pin 7) = v dd 3.58 14.3 5.0 20.0 10 mhz mhz mhz pin 4 input, or oscillator between pins 3 and 4 pin 12 duty ratio = 50% i/o pin capacitance item symbol condition min. typ. max. unit remarks input pin output pin input/output pins c in c out c i/o v dd = v i = 0v, f = 1mhz v dd = v i = 0v, f = 1mhz v dd = v i = 0v, f = 1mhz 9 11 11 pf pf pf
? 5 CXD2131Q description of pins and electrical characteristics analog section (v dd = 5.0v, v ss = 0v, ta = 25 c) pin no. symbol equivalent circuit description 2 4 2 5 a v d d a v s s 24 iset1 bias setting pins. connect to av dd with 33k . 25 iset2 27 vin11 chip clamp, sync separation input. 29 vin21 28 vin12 pedestal clamp, data slicer input. 30 vin22 31 vin3 input/output pins for encoder. on resistance value between pins 31 and 32: max. 350 . 32 26 1 vout 2 7 2 9 a v d d a v s s a v d d a v s s 2 8 3 0 a v d d a v s s 3 1 3 2 a v d d a v s s a v d d a v s s av dd av ss not connected to digital power supply (pin 8) inside the ic. not connected to digital ground (pins 5 and 19) inside the ic. analog power supply. connect power supply low in noise from the digital system. analog ground. connect to same potential as digital ground (pins 5 and 19). c l a m p v o l t a g e 1 . 5 v c l a m p v o l t a g e 1 . 5 v
? 6 CXD2131Q 1. description of video aspect ratio identification signal transfer method (aspect ratio identification) as shown in the table below, video aspect ratio identification signal consists of 14-bit data, to which a 6-bit crcc is appended for a total of 20 bits. on an ntsc video signal, this information is carried on lines 20 and 283 of the vertical blanking interval. bit-no. word0 a b 1 2 3 4 5 6 transfer aspect ratio pictorial representation format undefined full mode (16 : 9) letter-box 4 : 3 normal discrimination information about the video signal and any other signal (audio signal, etc.) incident to the video and transferred simultaneously. word1 word2 4-bit width 4-bit width word 0 dependent discrimination signal word 0 dependent discrimination signal, information, etc. description ? ? (from provisional standard of eiaj, cpx-1204) 2. decoding the CXD2131Q has a decoding function which extracts video aspect ratio identification signals from the video signal. a 1vp-p video signal is input. there are two video signal input systems, ch1 (pins 27 and 28) and ch2 (pins 29 and 30). these are switched and decoded one at a time. as shown below, the decoding circuit and crcc check circuit are in one system, but there are two systems for the data validity criterion circuit and decoding result, for each channel. this means that even when one channel is being decoded, the decoding result for the other channel is held. isel performs channel switching. isel is set by microcomputer transmission or by pins. for ch1, isel = ?? and for ch2, isel = ?? t i m i n g s i g n a l g e n e r a t o r d a t a s l i c e r s y n c s e p a r a t o r d a t a s l i c e r d e c o d e c i r c u i t c r c c c h e c k l a t c h l a t c h d a t a v a l i d i t y c r i t e r i o n d a t a v a l i d i t y c r i t e r i o n 1 4 d e c o d i n g r e s u l t o u t p u t d a t a v a l i d i t y c r i t e r i o n o u t p u t c r c c c h e c k o u t p u t c h 1 i n p u t c h 2 i n p u t c h 1 / c h 2 s w i t c h i n g 1 4 s y n c s e p a r a t o r further, the composite sync signal of the channel being decoded can be monitored at csyc (pin 16) and the crcc check result can be monitored at crco (pin 15), even during decoding. also, when tst1 (pin 22) is held at high level, the data slice result for decoding can be monitored at o164 (pin 21). for the decoding operation, the range of the scanning lines to be decoded on the video signal can be switched by lnj1. lnj1 can be set by microcomputer control or by pins. when lnj1 is ?? only lines 20 and 283 are decoded, and when lnj1 is ?? one line on each side of lines 20 and 283 are decoded in addition.
? 7 CXD2131Q 3. encoding the CXD2131Q has an encoding function which adds video aspect ratio identification signals to the video signal. a 1vp-p video signal is encoded. an encoded video signal is output on vout (pin 32) by inputting the video signal input to the decoding function ch2 side to vin3 (pin 31) as well. when this encoding function is used, decoding input must be switched to ch2. encoding is controlled by oe, which is set by microcomputer control or by pins. encoding is off when oe is ?? and the input video signal is output as it is from vout (pin 32). for example, even when ch1 is decoding, the video signal input to ch2 can be obtained as it is at vout if oe is set to ?? 4. clock the CXD2131Q requires an fsc (= 3.579545mhz) or 4 fsc clock. when selxt (pin 2) is ??the clock is fsc; when it is ?? the clock is 4 fsc. connect xi (pin 4) and xo (pin 3) when using a crystal oscillator. input to xi for external input. 5. settings and data input/output there are three methods of performing the CXD2131Q settings and data input/output: direct setting by pins without using a microcomputer, the 4-line microcomputer serial interfaces, and i 2 c bus interface. 5-1. microcomputer-free mode direct input/output by pins, without using a microcomputer, can be carried out by setting mcon (pin 9) to?? in this case, only the first 2 bits of the total 14 bits of video aspect ratio identification signals are input or output. the decoding result is obtained at o164 (pin 21) and olbx (pin 20). the data for encoding is input to i164 (pin 6) and prtc/ilbx (pin 7). for the various settings, decode channel switching isel is input to sclk (pin 12), decode scanning line range switching lnj1 to srin (pin 13) and encode operation existence oe to xcs (pin 11). connect srot (pin 10), scl (pin 17) and sda (pin 18), which are unused, to vss. 5-2. 4-line serial interface setting and data input/output can be carried out by microcomputer serial interface when mcon (pin 9) is set at ??and prtc (pin 7) is set at ?? in this case, all 14 bits of video aspect ratio identification signals are input or output. serial data from the microcomputer of serial transmission connects to srin (pin 13), the serial clock to sclk (pin 12), and select to xcs (pin 11). serial data to the microcomputer is output at srot (pin 10). connect scl (pin 17) and sda (pin 18), which are unused, to vss. serial interface bit configuration is shown in the following figures.
? 8 CXD2131Q com ? cxd2131 w o r d 0 b i t 1 , b i t 2 d o n t c a r e w o r d 0 b i t 3 t o b i t 6 w o r d 1 w o r d 2 i s e l i r e s o e t e s t l n j 1 d o n t c a r e s i e n v i d e o a s p e c t r a t i o i d e n t i f i c a t i o n s i g n a l s c a r r i e d o n v i d e o s i g n a l ( e n c o d e d ) d e c o d e i n p u t s w i t c h i n g e n c o d e o n / o f f d e c o d e / e n c o d e ; " 1 " = c i r c u i t r e s e t , n o t s t a n d b y e x i s t e n c e o f 1 l i n e b e f o r e a n d a f t e r d e c o d e r a n g e n o r m a l l y " 0 " v a l i d i t y / i n v a l i d i t y o f a l l s e t t i n g d a t a ; " 1 " = v a l i d 4 b i t 2 b i t 4 b i t 1 b i t 1 b i t 1 b i t 2 b i t 4 b i t 1 b i t 1 b i t 1 b i t 2 b i t t o t a l 2 4 b i t s cxd2131 ? com w o r d 0 b i t 1 , b i t 2 w o r d 0 b i t 3 t o b i t 6 w o r d 1 w o r d 2 4 b i t 2 b i t 1 b i t 1 b i t t o t a l 1 6 b i t s v a l i d c r c c 4 b i t 4 b i t " 1 " w h e n c r c c r e s u l t i s c o r r e c t " 1 " w h e n d a t a v a l i d i t y c r i t e r i o n r e s u l t i s c o r r e c t v i d e o a s p e c t r a t i o i d e n t i f i c a t i o n s i g n a l s e x t r a c t e d f r o m v i d e o s i g n a l ( d e c o d e d ) v i d e o a s p e c t r a t i o i d e n t i f i c a t i o n s i g n a l s e x t r a c t e d f r o m v i d e o s i g n a l ( d e c o d e d ) fig. 1 (a). bit configuration of 4-line serial interface x c s t d s o t t z s r o s c l k s r i n s r o t t z s r o t s u s c t h d s c h i - z h i - z d o n t c a r e fig. 1 (b). 4-line serial interface timing set-up to srin sclk rising edge hold to srin sclk rising edge delay from srot sclk falling edge three-state control delay by srot xcs item symbol condition t susc t hdsc t dsot t zsro cload = 20pf rload = 2k 10 10 40 40 ns ns ns ns min. typ. max. unit
? 9 CXD2131Q 5-3. i 2 c bus interface setting and data input/output can be carried out by microcomputer i 2 c bus interface when mcon (pin 9) is set at ??and prtc (pin 7) is set at ?? in this case, all 14 bits of video aspect ratio identification signals are input or output. this i 2 c bus corresponds to standard mode. i 2 c address is 40h. i 2 c bus data connects to sda (pin 18) and i 2 c bus clock to scl (pin 17). connect srin (pin 13), sclk (pin 12) and xcs (pin 11), which are unused, to vss. and leave srot (pin 10) open. i 2 c bus interface bit configuration is shown in fig. 2. com ? cxd2131 w o r d 0 b i t 1 , b i t 2 d o n t c a r e w o r d 0 b i t 2 t o b i t 6 w o r d 1 w o r d 2 i s e l i r e s o e t e s t l n j 1 d o n t c a r e v i d e o a s p e c t r a t i o i d e n t i f i c a t i o n s i g n a l s c a r r i e d o n v i d e o s i g n a l ( e n c o d e d ) d e c o d e i n p u t s w i t c h i n g e n c o d e o n / o f f d e c o d e / e n c o d e ; " 1 " = c i r c u i t r e s e t , n o t s t a n d b y e x i s t e n c e o f 1 l i n e b e f o r e a n d a f t e r d e c o d e r a n g e n o r m a l l y " 0 " 4 b i t 2 b i t 4 b i t 1 b i t 1 b i t 2 b i t 4 b i t 1 b i t 1 b i t 1 b i t 3 b i t t o t a l 2 4 b i t s cxd2131 ? com w o r d 0 b i t 1 , b i t 2 w o r d 0 b i t 3 t o b i t 6 w o r d 1 w o r d 2 4 b i t 2 b i t 1 b i t 1 b i t t o t a l 1 6 b i t s v a l i d c r c c 4 b i t 4 b i t " 1 " w h e n c r c c r e s u l t i s c o r r e c t " 1 " w h e n d a t a v a l i d i t y c r i t e r i o n r e s u l t i s c o r r e c t v i d e o a s p e c t r a t i o i d e n t i f i c a t i o n s i g n a l s e x t r a c t e d f r o m v i d e o s i g n a l ( d e c o d e d ) v i d e o a s p e c t r a t i o i d e n t i f i c a t i o n s i g n a l s e x t r a c t e d f r o m v i d e o s i g n a l ( d e c o d e d ) fig. 2. bit configuration of i 2 c bus interface
? 10 CXD2131Q the CXD2131Q i 2 c bus interface has a subaddress function. with the subaddress function, only the bytes after setting has started are set. there is no subaddress function at the read side. i 2 c a d d r e s s s e l t o l n j 1 w o r d 0 b y t e 0 s u b a d d r e s s w o r d 1 , 2 b y t e 1 b y t e 2 w h e n s u b a d d r e s s = 0 d u r i n g s e t t i n g i 2 c a d d r e s s s e l t o l n j 1 b y t e 2 s u b a d d r e s s w h e n s u b a d d r e s s = 2 d u r i n g s e t t i n g i 2 c a d d r e s s w o r d 1 , 2 w o r d 0 c r c c , v a l i d n o s u b a d d r e s s d u r i n g r e a d fig. 3. description of i 2 c bus and subaddress
? 11 CXD2131Q application circuit (4-line microcomputer i/f for vcr, with encoder) note) jp1 in the figure above normally is not connected. it is only connected when monitoring slicer output from pin 21, when checkin g the circuit or the like. v d d = 5 . 0 v t i m i n g s i g n a l g e n e r a t o r d e c o d e r s y n c s e p a r a t o r c h i p c l a m p p e d e s t a l c l a m p d a t a s l i c e r s y n c s e p a r a t o r c h i p c l a m p p e d e s t a l c l a m p d a t a s l i c e r e n c o d e r v c r 4 - l i n e i n t e r f a c e i 2 c b u s i n t e r f a c e c x d 2 1 3 1 q 1 5 1 6 2 0 2 1 2 6 2 5 2 4 1 2 3 4 5 6 3 9 h 3 3 k 3 3 k 2 7 2 8 2 9 3 0 3 1 3 2 1 5 0 0 p 1 0 0 1 1 1 5 0 0 p 1 0 0 1 1 2 2 0 0 . 1 4 7 / 1 6 1 0 k 1 5 k 5 1 0 8 2 1 0 / 1 6 v i n 1 1 0 k 1 5 k 8 2 1 0 / 1 6 v i n 2 5 . 1 k 1 . 1 k 3 3 / 1 6 v o u t 1 1 0 5 1 0 5 1 0 k 1 0 k j p 1 2 3 2 2 1 7 1 8 1 9 1 4 s r i n s c l k x c s s r o t t o m i c r o c o m p u t e r 0 . 1 3 . 5 8 m 2 2 p 2 2 p 7 8 9 4 7 / 1 6 1 3 1 0 1 1 1 2 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 12 CXD2131Q application circuit (with i 2 c bus, no encoder) note) jp1 in the figure above normally is not connected. it is only connected when monitoring slicer output from pin 21, when checkin g the circuit or the like. v d d = 5 . 0 v t i m i n g s i g n a l g e n e r a t o r d e c o d e r s y n c s e p a r a t o r c h i p c l a m p p e d e s t a l c l a m p d a t a s l i c e r s y n c s e p a r a t o r c h i p c l a m p p e d e s t a l c l a m p d a t a s l i c e r e n c o d e r v c r 4 - l i n e i n t e r f a c e i 2 c b u s i n t e r f a c e c x d 2 1 3 1 q 1 5 1 6 2 0 2 1 2 6 2 5 2 4 1 2 3 4 5 3 9 h 3 3 k 3 3 k 2 7 2 8 2 9 3 0 3 1 3 2 1 5 0 0 p 1 0 0 1 1 1 5 0 0 p 1 0 0 1 1 0 . 1 4 7 / 1 6 2 2 k 3 3 k 1 k 8 2 1 0 / 1 6 v i n 1 2 2 k 3 3 k 8 2 1 0 / 1 6 v i n 2 1 k 1 0 k j p 1 2 3 2 2 1 7 1 8 1 9 1 4 d a t a c l o c k i 2 c - b u s 0 . 1 3 . 5 8 m 2 2 p 2 2 p 8 9 4 7 / 1 6 1 3 1 0 1 1 1 2 6 7 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 13 CXD2131Q package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y 3 2 p i n q f p ( p l a s t i c ) 9 . 0 0 . 2 7 . 0 0 . 1 1 . 5 0 . 1 5 ( 8 . 0 ) 0 . 1 0 . 1 + 0 . 2 + 0 . 3 5 + 0 . 3 0 . 5 0 0 . 1 2 7 0 . 0 5 + 0 . 1 0 t o 1 0 0 . 8 0 . 3 0 . 1 + 0 . 1 5 1 8 9 3 2 1 6 1 7 2 4 2 5 m 0 . 2 4 0 . 2 g q f p - 3 2 p - l 0 1 q f p 0 3 2 - p - 0 7 0 7 0 . 1

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